The AT90S1200 is a low-power CMOS 8-bit microcontroller based on an enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AT90S1200 core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The architecture supports high level languages efficiently as well as extremely dense assembler code programs. The AT90S1200 provides the following features: 1K bytes of Downloadable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32 general purpose working registers, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the registers, timer/counter, watchdog and interrupt system to continue functioning. The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

The device is manufactured using high density non-volatile memory technology. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with Downloadable Flash on a monolithic chip, the AT90S1200 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90S1200 is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

PIN DESCRIPTIONS

*Optional. XTLIN and XTLOUT are input and output, respectively, of an inverting amplifier which can be configured for use with an external quartz crystal or ceramic resonator. In this case two capacitors (i.e. 47pf) are wired from these pins to ground in addition to the crystal. To drive the device from an external clock source, XTLOUT should be left unconnected while XTLIN is driven.

VCC Supply voltage pin.

GND Ground pin.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pullups (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output buffers can sink 20mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and are exter-nally pulled low, they will source current (IIL ) if the internal pullups are activated. Port B also serves the functions of various special features.

Port D (PD6..PD0)

Port D has seven bi-directional I/O pins with internal pullups, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (IIL) if the pullups are activated. Port D also serves the functions of various special features.

RESET

Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device.

XTLIN

Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Not used if internal oscillator selected.

XTLOUT

Output from the inverting oscillator amplifier Not used if internal oscillator selected.

On-Chip RC Oscillator

An on-chip RC oscillator running at a fixed frequency of about 1 MHz can be selected as the MCU clock source. If enabled, the AT90S1200 can operate with no external components. A control bit - RCEN in the Flash Memory selects the on-chip RC oscillator as the clock source when programmed. The AT90S1200 is normally shipped with this bit programmed (1). The RCEN-bit can be changed by parallel programming only. When using the on-chip RC oscillator for serial program downloading, the RCEN bit must programmed in parallel programming mode first.

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. The AT90S1200 uses a Harvard architecture concept with separate memories and buses for program and data memories. The program memory is accessed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory.

With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AT90S1200 instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a 3 level deep hardware stack dedicated for subroutines and interrupts.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The memory spaces in the AT90S1200 architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt address vector the higher priority.

The General Purpose Register File

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or on a single register apply to the entire register file.

The ALU - Arithmetic Logic Unit

The high-performance AT90S1200 ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logic and bit-functions. Some microcontrollers in the AT90S1200 product family feature a hardware multiplier in the arithmetic part of the ALU.

The Downloadable Flash Program Memory

The AT90S1200 contains 1K bytes on-chip downloadable Flash memory for program storage. Since all instructions are single 16-bit words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1000 write/ erase cycles.

The AT90S1200 Program Counter is 9-bit wide, thus addressing the 512 words Flash program memory.

The Program and Data Addressing Modes

The AT90S1200 Enhanced RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the AT90S1200. OP means the operation code part of the instruction word.

The operand is contained in register d (Rd).

The register accessed is the one pointed to by the Z-register (R30).

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O DIRECT

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL

Program execution continues at address PC + k. The relative address k is in the range from -2K to +(2K - 1).

Subroutine and Interrupt Hardware Stack

The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The hardware stack is 9 bit wide and stores the Program Counter - PC - return address while subroutines and interrupts are executed. RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1-2 are pushed one level deeper in the stack.

When a RET or RETI instruction is executed the returning PC is fetched from the stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack. If more than 3 subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten.

The EEPROM Data Memory

The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is the EEPROM address register, the EEPROM data register, and the EEPROM control register.

INSTRUCTION EXECUTION TIMING

This section describes the general access timing concepts for instruction execution and internal memory access. The AT90S1200 CPU is driven by the System Clock, directly generated from the external clock crystal for the chip. No internal clock division is used.

The parallel instruction fetches and instruction executions are enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

I/O

Address Name Function

$3F SREG Status REGister

$3B GIMSK General Interrupt MaSK register

$39 TIMSK Timer/Counter Interrupt MaSK register

$38 TIFR Timer/Counter Interrupt Flag register

$35 MCUCR MCU general Control Register

$33 TCCR0 Timer/Counter 0 Control Register

$32 TCNT0 Timer/Counter 0 (8-bit)

$21 WDTCR Watchdog Timer Control Register

$1E EEAR EEPROM Address Register

$1D EEDR EEPROM Data Register

$1C EECR EEPROM Control Register

$18 PORTB Data Register, Port B

$17 DDRB Data Direction Register, Port B

$16 PINB Input Pins, Port B

$12 PORTD Data Register, Port D

$11 DDRD Data Direction Register, Port D

$10 PIND Input Pins, Port D

$08 ACSR Analog Comparator Control and Status Register

All the different AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

The different I/O and peripheral control registers are explained in the following sections.

THE STATUS REGISTER - SREG

The AT90S1200 status register - SREG - at I/O space location $3F is defined as:

Bit 7 6 5 4 3 2 1 0

$3F I T H S V N Z C

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bit 7 - I : Global Interrupt Enable:

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the interrupt mask registers - GIMSK/TIMSK. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled, independent of the GIMSK/TIMSK values. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.

Bit 6 - T : Bit Copy Storage:

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

Bit 5 - H : Half Carry Flag:

The half carry flag H indicates a half carry in some arithmetic operations.

Bit 4 - S : Sign Bit, S = N^V:

The S-bit is always an exclusive or between the negative flag N and the twos complement overflow flag V.

Bit 3 - V : Two's Complement Overflow Flag:

The twos complement overflow flag V supports two's complement arithmetics.

Bit 2 - N : Negative Flag:

The negative flag N indicates a negative result after the different arithmetic and logic operations.

Bit 1 - Z : Zero Flag:

The zero flag Z indicates a zero result after the different arithmetic and logic operations.

Bit 0 - C : Carry Flag:

The carry flag C indicates a carry in an arithmetic or logic operation.

Reset and Interrupt Handling

The AT90S1200 provides 3 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0 etc.

Table 2. Reset and Interrupt Vectors

Vector Address Source Interrupt Definition

1 $000 RESET Hardware Pin and Watchdog Reset

2 $001 INT0 External Interrupt Request 0

4 $002 TIMER0,OVF0 Timer/Counter0 Overflow

5 $003 ANA_COMP Analog Comparator

The most typical and general program setup for the Reset and Interrupt Vector Addresses are:

Address Code Comments

$000 rjmp RESET ; Reset handle

$001 rjmp EXT_INT0 ; IRQ0 handle

$002 rjmp TIM0_OVF ; Timer0 overflow handle

$003 rjmp ANA_COMP ; Analog Comparator Handle

$004 MAIN: <instr> xxx ; Main program start

RESET SOURCES

The AT90S1200 has three sources of reset:

- Power-On Reset. The MCU is reset when a supply voltage is applied to the VCC and GND pins.

- External Reset. The MCU is reset when a low level is present on the RESET pin for more than two XTAL cycles

- Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. Table 3 defines the timing and electrical parameters of the reset circuitry. Note that Power On Reset timing is clocked by the internal RC oscillator. Refer to characterization data for RC oscillator frequency at other VCC voltages.

Table 3. Reset Characteristics (VCC = 5.0V)

Symbol Parameter Min Typ Max Units

VPOT Power-On Reset Threshold Voltage 1.8 2 2.2 V

VRST Pin Threshold Voltage VCC/2 V

tPOR Power-On Reset Period 2 3 4 ms

tTOUT Reset Delay Time-Out Period 11 16 21 ms

POWER-ON RESET

A Power-On Reset (POR) circuit ensures that the device is not started until VCC has reached a safe level. An internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time. The total reset period is the Power-On Reset period - tPOR + the Delay Time-out period - tTOUT.

As the RESET pin is pulled high by an on-chip resistor, the pin can be left unconnected if no external reset is required. Connecting RESET to VCC will have the same effect. By holding the RESET pin low for a period after VCC has been applied, the Power-On Reset period can be extended.

EXTERNAL RESET

An external reset is generated by a low level on the pin. The pin must be held low for at least two crystal clock cycles. When it reaches the Reset Threshold Voltage - VRST on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired.

WATCHDOG RESET

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT.

INTERRUPT HANDLING

The AT90S1200 has two Interrupt Mask control registers GIMSK - General Interrupt MASK register - at I/O space address $3B and the TIMSK - Timer/Counter Interrupt MaSK register at I/O address $39. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI – is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.

THE GENERAL INTERRUPT MASK REGISTER - GIMSK

Bit 7 6 5 4 3 2 1 0

$3B - INT0 - - - - - -

Read/Write R R/W R R R R R R

Initial value 0 0 0 0 0 0 0 0

Bit 7 - Res : Reserved bit:

This bit is a reserved bit in the AT90S1200 and always read zero.

Bit 6 - INT0 : External Interrupt Request 0 Enable:

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. INT0 can be activated even if the pin is configured as an output.

Bits 5..0 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read as zero.

THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK

Bit 7 6 5 4 3 2 1 0

$39 - - - - - - TOIE0 -

Read/Write R R R R R R R/W R

Initial value 0 0 0 0 0 0 0 0

Bits 7..2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.

Bit 1 - TOIE0 : Timer/Counter0 Overflow Interrupt Enable:

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 0 - Res: Reserved bit:

This bit is a reserved bit in the AT90S1200 and always reads zero.

THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR

Bit 7 6 5 4 3 2 1 0

$38 - - - - - - TOV0 -

Read/Write R R R R R R R/W R

Initial value 0 0 0 0 0 0 0 0

Bits 7..2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.

Bit 1 - TOV0 : Timer/Counter0 Overflow Flag:

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

Bit 0 - Res: Reserved bit:

This bits is a reserved bit in the AT90S1200 and always reads zero.

EXTERNAL INTERRUPTS

The external interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or level. This is set up as described in the specification for the MCU control register - MCUCR. When INT0 is level triggered, the interrupt is pending as long as INT0 is held low.

The interrupt is triggered even if INT0 is configured as an output. This provides a way to generate a software interrupt. The interrupt flag can not be directly accessed by the user. If an external edge triggered interrupt is suspected to be pending, the flag can be cleared as follows.

1. Disable the external interrupt by clearing the INT0 flag in GIMSK.

2. Select level triggered interrupt.

3. Select desired interrupt edge.

4. Re-enable the external interrupt by setting INT0 in GIMSK.

INTERRUPT RESPONSE TIME

The interrupt execution response for all the enabled AT90S1200 interrupts is 4 clock cycles minimum. After the 4 clock cycles the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (9 bits) is pushed onto the Stack. The vector is a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (9 bits) is popped back from the Stack. When AT90S1200 exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register - SREG - is not handled by the AT90S1200 hardware, neither for interrupts nor for subroutines. For the routines requiring a storage of the SREG, this must be performed by user software. Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if more than 3 nested subroutines and interrupts are executed, only the most recent 3 return addresses are stored.

THE MCU CONTROL REGISTER - MCUCR

The MCU Control Register contains general microcontroller control bits for general MCU control functions.

Bit 7 6 5 4 3 2 1 0

$35 - - SE SM - - ISC01 ISC00

Read/Write R R R/W R/W R R R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bits 7, 6 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.

Bit 5 - SE : Sleep Enable:

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

Bit 4 - SM : Sleep Mode:

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph Sleep Modes below.

Bits 3, 2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.

Bits 1, 0 - ISC01, ISC00 : Interrupt Sense Control 0 bit 1 and bit 0:

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the GIMSK register is set. The level and edges on the external INT0 pin that activate the interrupt are defined as:

Table 4. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Reserved

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

Note: When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are changed.

SLEEP MODES

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and the I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector. Note that if a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the oscillator start-up time of 16 ms. Otherwise, the interrupt flag may return to zero before the MCU starts executing.

IDLE MODE

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup from the Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status register - ACSR. This will reduce power consumption during Idle Mode.

POWER DOWN MODE

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external oscillator is stopped. The user can select whether the watchdog shall be enabled during power-down mode. If the watchdog is enabled, it will wake up the MCU when the Watchdog Time-out period expires. If the watchdog is disabled, only an external reset or an external level triggered interrupt can wake up the MCU.

TIMER / COUMTER

The AT90S1200 provides one general purpose 8-bit Timer/Counter. The Timer/Counter gets the prescaled clock from the 10-bit prescaling timer. The Timer/Counter can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.

The Timer/Counter Prescaler

The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the Timer/Counter, added selections as CK, external source and stop, can be selected as clock sources.

The 8-bit Timer/Counter0

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register - TCCR0. The overflow status flag is found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register - TIMSK.

When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.

THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0

Bit 7 6 5 4 3 2 1 0

$33 - - - - - CS02 CS01 CS00

Read/Write R R R R R R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bits 7..3 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.

Bits 2,1,0 - CS02, CS01, CS00:

Clock Select0, bit 2,1 and 0: The Clock Select0 bits 2,1 and 0 define the

prescaling source of Timer0.

Table 5. Clock 0 Prescale Select

CS02 CS01 CS00 Description

0 0 0 Stop, the Timer/Counter0 is stopped.

0 0 1 CK

0 1 0 CK / 8

0 1 1 CK / 6 4

1 0 0 CK / 256

1 0 1 CK / 1024

1 1 0 External Pin T0, falling edge

1 1 1 External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual data direction control register (cleared to zero gives an input pin).

Bits 5..3 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.

THE TIMER COUNTER 0 - TCNT0

Bit 7 6 5 4 3 2 1 0

$32 MSB LSB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.

THE WATCHDOG TIMER

The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted from 16 to 2048 cycles.

The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the maximum period between two WDR instructions to avoid that the Watchdog Timer resets the MCU. If the reset period expires without another WDR instruction, the AT90S1200 resets and executes from the reset vector.

THE WATCHDOG TIMER CONTROL REGISTER - WDTCR

Bit 4 3 2 1 0

$21 WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R/W R/W R/W R/W

Initial value 0 0 0 0 0

Bits 7..4 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and will always read as zero.

Bit 3 - WDE : Watchdog Enable:

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled.

Bits 2..0 - WDP2..0 : Watchdog Timer Prescaler 2,1 and 0:

The WDP2..0 determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 6.

Table 6. Watchdog Timer Prescale Select (Typical Values at VCC = 5.0V)

WDP2 WDP1 WDP0 Timeout Period

0 0 0 16 cycles

0 0 1 32 cycles

0 1 0 64 cycles

0 1 1 128 cycles

1 0 0 256 cycles

1 0 1 512 cycles

1 1 0 1024 cycles

1 1 1 2048 cycles

EEPROM READ/WRITE

The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the VCC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. An EEPROM brown-out detection prevents writing to the EEPROM if VCC is below a certain level.

When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed.

THE EEPROM ADDRESS REGISTER - EEAR

Bit 5 4 3 2 1 0

$1E EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0

Read/Write R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0

Bit 7,6 - Res : Reserved bits:

These bits are reserved bit in the AT90S1200 and will always read as zero.

Bits 5..0 - EEAR..0 : EEPROM Address:

The EEPROM Address Register - EEAR specifies the EEPROM address in the 64-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63.

THE EEPROM DATA REGISTER - EEDR

Bit 7 6 5 4 3 2 1 0

$1D MSB LSB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bits 7..0 - EEDR7..0 : EEPROM Data:

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

THE EEPROM CONTROL REGISTER - EECR

Bit 1 0

$1C EEWE EERE

Read/Write R/W R/W

Initial value 0 0

Bits 7..2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and will always be read as zero.

Bit 1 - EEWE : EEPROM Write Enable:

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2.5ms at Vcc=5V and 4ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 - EERE : EEPROM Read Enable:

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for two cycles before the next instruction is executed.

THE ANALOG COMPARATOR

The analog comparator compares the input values on the positive pin PB0(AIN0) and the negative pin PB1 (AIN1). When the voltage on the positivepin PB0 (AIN0) is higher than the voltage on the negative pin PB1 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator's output can be set to trigger the Analog Comparator interrupt. The user can select Interrupt triggering on comparator output rise, fall or toggle.

THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER - ACSR

Bit 7 6 5 4 3 2 1 0

$08 ACD – ACO ACI ACIE - ACIS1 ACIS0

Read/Write R/W R R R/W R/W R R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bit 7 - ACD : Analog Comparator Disable

When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. It is most commonly used if power consumption during Idle Mode is critical, and wake-up from the analog comparator is not required. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

Bit 6 - Res : Reserved bit:

This bit is a reserved bit in the AT90S1200 and will always read as zero.

Bit 5 - ACO : Analog Comparator Output:

ACO is directly connected to the comparator output.

Bit 4 - ACI : Analog Comparator Interrupt Flag:

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

Bit 3 - ACIE : Analog Comparator Interrupt Enable:

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

Bit 2 - Res : Reserved bit:

This bit is a reserved bit in the AT90S1200 and will always read as zero.

Bits 1,0 - ACIS1, ACIS0 : Analog Comparator Interrupt Mode Select:

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 7.

Tabl e 7. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

0 1 Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.

I/O-PORTS

Port B

Port B is an 8-bit bi-directional I/O port.

Three data memory address locations are allocated for the Port B, one each for the Data Register - PORTB ($18), Data Direction Register - DDRB ($17) and the Port B Input Pins - PINB ($16). The Port B Input Pins address is read only, while the Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pullups. The Port B output buffers can sink 20mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current (I IL ) if the internal pullups are activated.

The Port B pins with alternate functions are shown in the following table:

Table 8. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB0 AIN0 (Analog comparator positive input)

PB1 AIN1 (Analog comparator negative input)

PB5 MOSI (Data input line for memory downloading)

PB6 MISO (Data output line for memory uploading)

When the pins are used for the alternate function, the DDRB and PORTB register has to be set according to the alternate function description.

THE PORTB DATA REGISTER - PORTB

Bit 7 6 5 4 3 2 1 0

$18 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

THE PORT B DATA DIRECTION REGISTER - DDRB

Bit 7 6 5 4 3 2 1 0

$17 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

THE PORT B INPUT PIN ADDRESS - PINB

Bit 7 6 5 4 3 2 1 0

$16 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0

Read/Write R R R R R R R R

Initial value Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the pins are read.

PORTB AS GENERAL DIGITAL I/O

All 8 bits in port B are equal when used as digital I/O pins.

PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) and the pin is configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTBn has to be cleared (zero) or the pin has to be configured as an output pin.

Table 9. DDBn Effect on PORTB Pins

DDBn PORTBn I/O Pullup Comment

0 0 Input No Tri-state (Hi-Z)

0 1 Input Yes PBn will source current (I IL ) if ext. pulled low.

1 0 Output No Push-Pull Zero Output

1 1 Output No Push-Pull One Output2-31

n: 7,6...0, pin number.

ALTERNATE FUNCTIONS OF PORTB

The alternate pin functions of Port B are:

SCK - PORTB, Bit 7:

Clock input pin for Memory up/downloading.

MISO - PORTB, Bit 6:

Data output pin for Memory uploading.

MOSI - PORTB, Bit 5:

Data input pin for Memory downloading.

AIN1 - PORTB, Bit 1:

Analog Comparator Negative Input. When configured as an input (DDB1 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB1 is cleared (zero)), this pin also serves as the negative input of the on-chip analog comparator.

AIN0 - PORTB, Bit 0:

Analog Comparator Positive Input. When configured as an input (DDB0 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB0 is cleared (zero)), this pin also serves as the positive input of the on-chip analog comparator.

Port D

Three data memory address locations are allocated for the Port D, one each for the Data Register - PORTD ($12), Data Direction Register - DDRD ($11) and the Port D Input Pins - PIND ($10). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write.

Port D has seven bi-directional I/O pins with internal pullups, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (I IL ) if the pullups are activated. Some Port D pins have alternate functions as shown in the following table:

Table 10. Port D Pins Alternate Functions

Port Pin Alternate Function

PD2 INT0 (External interrupt 0 input)

PD4 T0 (Timer/Counter 0 external input)

THE PORTD DATA REGISTER - PORTD

Bit 6 5 4 3 2 1 0

$12 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Read/Write R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0

THE PORT D DATA DIRECTION REGISTER - DDRD

Bit 6 5 4 3 2 1 0

$11 DD6 DD5 DD4 DD3 DD2 DD1 DD0

Read/Write R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0

THE PORT D INPUT PINS ADDRESS - PIND

Bit 6 5 4 3 2 1 0

$10 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0

Read/Write R R R R R R R

Initial value Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the PORTD Data Latch is read, and when reading PIND, the logical values present on the pins are read.

PORTD AS GENERAL DIGITAL I/O

PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PORTDn is set (one) when DDDn is configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTDn bit has to be cleared (zero) or the pin has to be configured as an output pin.

Table 11. DDDn Bits Effect on Port D Pins

DDDn PORTDn I/O Pullup Comment

0 0 Input No Tri-state (Hi-Z)

0 1 Input Yes PDn will source current (I IL ) if ext. pulled low.

1 0 Output No Push-Pull Zero Output

1 1 Output No Push-Pull One Output

n: 6...0, pin number.

ALTERNATE FUNCTIONS FOR PORTD

The alternate functions of Port D are:

T0 - PORTD, Bit 4:

T0, Timer/Counter0 clock source. See the Timer description for further details.

INT0 - PORTD, Bit 2:

INT0, External Interrupt source 0. See the interrupt description for further details.

ABSOLUTE MAXIMUM RATINGS

Operating Temperature ........................ -55C to +125C

NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature..................................... -65C to +150C

Voltage on any Pin except RESET with respect to Ground . -1.0V to +7.0V

Maximum Operating Voltage............................... 6.6VDC

Current per I/O Pin..................................... 40.0 mA DC

Current VCC and GND Pins................................ 140.0 mA

DC CHARACTERISTICS

TA = -40C to 85C, VCC = 2.7V to 6.0V (unless otherwise noted)

Under steady state (non-transient) conditions, IOL must be externally limited:

Maximum IOL per port pin: 20mA

Maximum total IOL for all output pins: 80mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

Minimum VCC for Power Down is 2V.

Value tested to 45C

Symbol Parameter Conditions Min Typ Max Units

VIL Input Low Voltage -0.2 .2 VCC-0.1 V

VIH Input High Voltage (Ex. XTLIN, RESET) .2VCC .9 VCC+.5 V

VIH1 Input High Voltage (XTLIN, RESET) 0.7VCC VCC+.5 V

VOL Output Low Voltage IIL=25mA VCC=5V 0.5 V

VOH Output High Voltage IOH=3mA VCC=5V VCC-.5 V

IOH Output Source Current VCC=5V VOH=4.5V 4 mA

IIL Output Sink Current VCC=5V VOL=0.5V 28 mA

RRST Reset Pull-Up Resistor 100 500 kohm

RI/O Pin Pull-Up Resistor 35 120 kohm

ICC Supply Current Active Mode 5V 4MHz 3.5 mA

Idle Mode 3V 4MHz 500 uA

Power Down WDT enabled 3V 10 15 uA

Power Down WDT disabled 3V 0.15 1 uA

VACIO Analog Comparator Offset Voltage VCC=5V 20 mV

IACLK Analog Comparator Leakage Current VIN=1V 10 nA

tACPD Analog Comparator Propagation Delay VCC=4V 500 ns

External Clock Drive

Symbol Parameter VCC=2.7V VCC=6.0V Units

Min Max Min Max

1/tCLCL Oscillator Frequency 0 4 0 12 MHz

tCLCL Clock Period 250 50.0 ns

tCHCX High Time 40 16.7 ns

tCLCX Low Time 40 16.7 ns

tCLCH Rise Time 10 4.15 ns

tCHCL Fall Time 10 4.15 ns